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XMEGA A [MANUAL]
8077I–AVR–11/2012
Figure 7-7.
Automatic run-time calibration.
The DFLL will stop when entering a sleep mode where the oscillators are stopped. After wake up, the DFLL will continue
with the calibration value found before entering sleep. The reset value of the DFLL calibration register can be read from
the production signature row.
When the DFLL is disabled, the DFLL calibration register can be written from software for manual run-time calibration of
the oscillator.
7.8
External Clock Source Failure Monitor
A built-in failure monitor is available for the external clock source. If the failure monitor is enabled for the external clock
source, and this clock source fails (the external clock source stops) while being used as the system clock, the device will:
Switch to run the system clock from the 2MHz internal oscillator
Reset the oscillator control register and system clock selection register to their default values
Set the failure detection interrupt flag for the failing clock source
Issue a non-maskable interrupt (NMI)
If the external clock source fails when not being used for the system clock, it is automatically disabled, and the system
clock will continue to operate normally. No NMI is issued. The failure monitor is meant for external clock sources above
32kHz. It cannot be used for slower external clocks.
When the failure monitor is enabled, it will not be disabled until the next reset.
The failure monitor is stopped in all sleep modes where the external clock source are stopped. During wake up from
sleep, it is automatically restarted.
The PLL and external clock source failure monitor settings are protected by the configuration change protection
mechanism, employing a timed write procedure for changing the settings. For details, refer to “Configuration Change
Protection” on page 13.
DFLL CNT
COMP
0
tRCnCREF
Frequency
OK
RCOSC fast,
CALA decremented
RCOSC slow,
CALA incremented
clkRCnCREF
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